|
Many Power Electronics engineers prefer a simpler design approach to using the boostbuck family of converters. Likewise, they would rather employ current-mode programming than voltage mode, and find it easier to trip on peak switch current than to rely on natural sampling. With this approach, choice of topology may be left to the individual designer. It matters little which switching converter is used, since one is simply pumping energy from a large bank of input capacitors to an even larger bank of output capacitors. The converter circuit topology is then just chosen to provide the right amount of in/outputs, distribute the switch stresses advantageously, provide convenient isolation, and correct for polarity reversals source v. load. All that is really necessary in such designs is good DC accuracy, which is provided by a DC integrator capacitor in the feedback compensation op amp, and high frequency switching to keep size down. P.S. This approach is for complete weenies  1) Minimizing magnetics is only a good idea to a cer-
tain point. Capacitors are, in general lightweight things, especially ceramic and film capacitors. But electrolytics are not! High current types require heavy metallization, making them heavier than one would think! So beware! The principal of diminishing returns reminds us that optimum performance in terms of ripple and size requires a just balance between inductive and capacitive filtering. 2) Excess output capacity is a fire hazard! In the event of a short in the load, the entire output capacitor bank will dump, even if the current limit trips! Sadly, most loads are not fused. [Note to self: maybe they should be?] A further disadvantage is that a load short that might otherwise merely trip the current limit will get worse, blowing more components until the C2 output capacitors are discharged, possibly even burning traces in the process! 3) The reason current mode programming is no good is simple. Though it has the benefit that damping is not used, and compensation is not necessary (only feedback), it is not magic! a) At any point in time, the duty cycle has to be something. It may be 0.1, 1/3, 0.4, 0.6 or whatever, but it must take a value from 0 to 1 each cycle. Different control schemes, including current mode programming, can do no more that choose D each cycle. Current mode programming theory assumes that the switch current will rise to a required level each interval. But, unfortunately, there is no guarantee that it can! The di/dt of any current in a switcher is limited by its inductor value, so switch current can only rise so fast.... Thus the current called for by the control loop may not be available before the end of Ts. What happens? The PWM hits Dmax, and the switching converter loses control. This is, in itself unacceptable, and the danger of chaotic behaviour is very real! The effect of these modes on the load and line, I will not go into!! b) Even in ordinary operation, a CMP converter has only a single pole response. This makes it trivial to compensate, but the slow rolloff means less gain-bandwidth = sluggish (RC) response. Thus one sacrifices performance for the designer's convenience, a poor tradeoff at best;( 4) Switch stress is a second order consideration. Parallelling FETs is possible if one needs power beyond the multi-kilowatt range already available in standard manufacture. Far better the engineer should have the minor headache associated with a second FET to drive, than that a customer should settle for inferior performance. And remeber that total switch stress is the same for all isolated converters! 5) Isolation is easy enough in the boostbuck converter. I mention elsewhere on this site that gapping the transformer with gap length ~ 0.003 x magnetic path length will work. Meanwhile, the volt-seconds indicated on the "Design Oriented DC Conditons" page are correct to use in designing the transformer itself (core size, number of turns, wire size, etc.) 6) Integral voltage feedback is silly, and useless. No load requires such accuracy, and an engineer is only fooling himself if he thinks Vout = 5.000000 volts matters to the customer's load. An op amp has 10E5 gain = 100dB = 1/1000th % DC error with IVF. No spec calls for this, and with good reason: step load/line regulation is far more difficult to achieve than DC regulation. In practice, any better than several percent transient regulation is unattainable without linear postregulation. 7) Though high frequency switching reduces the size and weight of a converter, little else of the story changes. Topological differences do not disappear as fs rises! Bucks and Boosts still have the same drawbacks and failings at 200Khz as they do at 20KHz. And the power they throw is no less! so the noise they make is the same as before. DC to daylight, the boostbuck is still superior! 8) The argument can be, and is sometimes made that holdup requirements in an offline PFC require a huge holdup capacitor, which component drives the design, making all loop response and performance arguments irrelevant. Unfortunately, most of the capacity of such a part is wasted, as the isolated Buck stage which follows is limited to D<1/2, so that the output voltage falls out of regulation long before the capacitor is drained. In a boostbuck PFC, the energy transfer cap can be drained all the way down to nothing, since V/Vg = D/D', which extends holdup time considerably! | Isolation of the Cuk Converter | Historical Perspective | | Return Home | Safety First | Lesson in Ethics | The Consequences of Bad Design | Real World Applications | Deals | e-mail me! | |
||
